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Notice how transistors Q 1 and Q 3 resemble the series-connected complementary pair from the inverter circuit. Of course, a separate pullup or pulldown resistor will be required for each gate input: It takes an applied voltage between gate and drain actually, between gate and substrate of the correct polarity to bias them on. Whereas TTL gates are restricted to power supply V cc voltages between 4. Because open-collector TTL outputs always sink, never source, current, pull up resistors are necessary when interfacing such an output to a CMOS gate input: When the channel substrate is made more positive than the gate gate negative in reference to the substratethe channel is enhanced and current is allowed between source and drain. You May Also Like: TTL, on the other hand, cannot function without some current drawn at all times, due to the biasing requirements of the bipolar transistors from which it is made. Note that the output of this gate never floats as is the case with the simplest TTL circuit: CMOS gate inputs are sensitive to static electricity.
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